Conventional gate length and gate dielectric scaling of complementary metal oxide semiconductor (CMOS) technology no longer produces the desired improvements in device performance. Parasitic resistances and capacitances are becoming a fundamental limiting factor to improving device performance with each new technology node. New materials and device architectures are thus required in order to overcome these fundamental scaling obstacles that degrade device performance.
One approach to overcome these effects is to increase the drive current of the metal-oxide-semiconductor field effect transistor (MOSFET) by increasing the mobility of the carriers in the channel. It is well known that the application of mechanical stress can substantially improve or degrade the mobility of electrons and holes in a semiconductor; however, it is also known that electrons and holes respond differently to the same type of stress. For example, the application of compressive stress in the longitudinal direction of current flow is beneficial for hole mobility, but detrimental for electron mobility. The application of tensile stress in the longitudinal direction is beneficial for electrons, but detrimental for holes.
State of the art technology currently uses stress nitride liners that are deposited after silicidation to apply longitudinal stress to the channel and therefore increase the current drive of CMOS devices. However, it is imperative to develop an integration scheme that allows the desired application of stress (compressive or tensile) on the appropriate devices (nFETs or pFETs) to maximize performance of CMOS technology. Unfortunately, the use of stress liners appears to be approaching limitations in the magnitude of stress that can be applied to the channel of CMOS devices.
In view of the above, there is a need for providing an alternative method to achieve higher magnitudes of stress in the channel (and therefore higher mobility) with the desired type of stress (compressive for pFET and tensile for nFET).